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Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication Systems

机译:基于帧的通信系统中用于鲁棒同步的高效互相关算法和体系结构

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摘要

Wireless communication in high-mobility environments is usually frame-based burst communication. Preamble sequences are generally used for time and frequency synchronization. Recently, Zadoff-Chu sequences have gained popularity for this purpose. In this paper, we propose an efficient cross-correlation-based algorithm and its implementation architecture for robust synchronization in systems with multiple preambles. The proposed method is well suited for systems experiencing carrier frequency offsets and operating in high-mobility environments. Synchronization is achieved by cross-correlation of local preamble replica with the segmented and decimated samples of the received preamble. The proposed architecture has been synthesized and implemented on Xilinx FPGA platform for validation and performance evaluation. The system-level simulation under additive white Gaussian noise, in Long-Term Evolution channels with frequency offsets and Doppler shifts, has also been carried out to find the efficacy of the proposed approach. The inherent parallelism of the proposed scheme results in a fast and energy-efficient implementation. One such implementation of the correlator structure in Xilinx FPGA is presented and is shown to have reduction in power consumption, capable of clocking higher clock speed with reduction in the usage of FPGA hardware resources such as DSP blocks and logic resulting in an overall reduction in energy consumption by , when compared to full-parallel cross-correlator-based synchronization.
机译:高移动性环境中的无线通信通常是基于帧的突发通信。前导序列通常用于时间和频率同步。最近,Zadoff-Chu序列已为此目的而流行。在本文中,我们提出了一种有效的基于互相关的算法及其实现架构,以在具有多个前同步码的系统中实现鲁棒同步。所提出的方法非常适合经历载波频率偏移并在高移动性环境中运行的系统。通过使本地前同步码副本与接收到的前同步码的分段和抽取样本互相关来实现同步。拟议的架构已经综合并在Xilinx FPGA平台上实现,以进行验证和性能评估。在具有频率偏移和多普勒频移的长期演进信道中,还进行了加性高斯白噪声下的系统级仿真,以发现该方法的有效性。所提出的方案的固有并行性导致快速且节能的实施。展示并展示了Xilinx FPGA中相关器结构的一种此类实现,并显示出这种功耗降低了,能够以更高的时钟速度提供时钟,同时减少了FPGA硬件资源(例如DSP块和逻辑)的使用,从而总体上降低了能耗与基于完全并行互相关器的同步相比,消耗。

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