Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage with High Random-Access Bandwidth and Large Storage Capacity

摘要

The recent trend towards highly parallel on-chi data processing, as e.g.in single-chip processors with parallel execution capability of multiple instructions, leads to the requirement of on-chip data storage with high random-access bandwidth, parallel access capa- bility and large capacity. The first two requirements call for the appli- cation of multi-ported memories. However, the conventional architec- ture, based on multi-port storage cells for each bit, cannot efficiently realize the large storage capacity, because cell area explodes due to a quadratic increase with port number (N).