首页> 外文期刊>IEICE Transactions on Electronics >CODEC Hardware Engines for a Low-Power Baseband DSP Macro
【24h】

CODEC Hardware Engines for a Low-Power Baseband DSP Macro

机译:低功耗基带DSP宏的CODEC硬件引擎

获取原文
获取原文并翻译 | 示例
       

摘要

The progress made in large-scale integration of the baseband circuits of digital cellular phones now makes it possible to implement a voice CODEC and its related functions in the baseband LSI rather than through a general-purpose digital signal processor. This paper describes an improved hardware solution that enables efficient application of the PSI-CELP CODEC-the most complex CODEC for mobile systems-to the PDC half-rate system through its implementation as a DSP macro in a low-voltage, large-scale LSI. Specific circuit blocks are added as hardware engines to a general-purpose DSP-oriented core. These specific engines were implemented as peripheral circuits for a DSP macro that can be used as a single DSP with an added I/O circuit and is suitable for use in future highly integrated mobile baseband chips. With the assistance of these hardware engines and some additional ALU instructions to achieve efficient programming, the machine speed required for the CODEC can be relatively slow, thus allowing the same architecture to be repeatedly used without needing to set the transistor threshold voltage too low even when the use of deeper sub-micron technologies require a chip to run at a lower supply voltage. We evaluated this DSP-macro architecture using a 0.35 μm CMOS technology test chip. Then we developed a commercial base version using 0.25 μm technology and verified that it can operate at 1.2V and that the PSI-CELP CODEC can be done at 40 MIPS with power consumption of 11 mW. We also verified that the circuit design can be applied up to 0.18 μm technology with a single threshold voltage of 0.3 V. Thus, the design of the DSP macro incorporating the hardware engines provides a great deal of flexibility that should allow its use in chips based on future technologies and the voice CODEC firmware can be effectively re-used. Although the DSP macro architecture was designed mainly through PSI-CELP application analysis, it can process other voice CODECs such as the AMR CODEC for third-generation mobile applications as well as some other mobile baseband functions such as channel CODECs. This approach can also be refined to permit its application to, for example, high-quality audio CODECs.
机译:现在,数字蜂窝电话的基带电路的大规模集成方面的进展使得有可能在基带LSI中而不是通过通用数字信号处理器来实现语音编解码器及其相关功能。本文介绍了一种改进的硬件解决方案,该解决方案通过将其作为低压大型LSI中的DSP宏来实现,从而能够将PSI-CELP CODEC(移动系统最复杂的CODEC)有效地应用于PDC半速率系统。 。将特定的电路块作为硬件引擎添加到面向DSP的通用内核中。这些特定的引擎被实现为DSP宏的外围电路,可以将其用作具有附加I / O电路的单个DSP,适用于将来的高度集成的移动基带芯片。借助这些硬件引擎和一些其他的ALU指令来实现高效的编程,CODEC所需的机器速度可能相对较慢,因此即使在以下情况下也无需将晶体管阈值电压设置得太低即可重复使用相同的体系结构使用更深的亚微米技术需要芯片以较低的电源电压运行。我们使用0.35μmCMOS技术测试芯片评估了这种DSP宏架构。然后,我们开发了使用0.25μm技术的商用基础版本,并验证了它可以在1.2V的电压下运行,并且PSI-CELP CODEC可以在40 MIPS的功耗下实现11 mW的功耗。我们还验证了该电路设计可以在0.3 V的单个阈值电压下应用高达0.18μm的技术。因此,结合了硬件引擎的DSP宏的设计提供了很大的灵活性,应该允许其在基于芯片的芯片中使用未来的技术和语音编解码器固件可以有效地重复使用。尽管DSP宏体系结构主要是通过PSI-CELP应用程序分析来设计的,但它可以处理其他语音编解码器,例如用于第三代移动应用程序的AMR CODEC,以及其他一些移动基带功能,例如通道编解码器。还可以完善此方法,以允许其应用于例如高质量音频编解码器。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号