首页> 外文期刊>IEICE Transactions on Electronics >Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems
【24h】

Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems

机译:线性时滞互连系统的无源降阶宏建模

获取原文
获取原文并翻译 | 示例
           

摘要

This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.
机译:本文提出了一种基于等价变换的状态空间时延系统描述的分布式互连方法。所提出的方法是获得线性时滞系统的被动降阶。统一的公式用于满足被动保存。本文给出了数学证明的细节和一些验证示例。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号