A Dual-Issue RISC Processor for Multimedia Signal Processing

摘要

This paper presents the architecture of a newly- developed dual-issue RISC processor, D10V, that achieves both high throughput signal processing capability and maintains flexibility for general purpose applications [1]. The RISC processor uses a 2-way VLIW architecture with a 32-bit wide instruction word. Two sub-instructions n a VLIW instruction are executed in two execution units in parallel. It also has several enhancements for signal processing. The processor includes pipelined multiply-and-accumulate instructions allowing a new multiply operation to be initiated every clock cycle and block repeat instructions for zero delay penalty loops.