A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme

摘要

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of + 1 = (1, 0), 0 = (0, 0), - 1 = (0, 1 ) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guar- antees the worst delay-time operation by the feedback loop of the rep- lica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant--binary addition/sub- traction circuit keep the area small. The architecture design avoids ex- tra calculation time for the post processes, whose main role is to pro- duce the floating-point status flags. The FDIV core using proposed technologies operates at 42.1 ns with 0.35 μm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730 μm x 910 pm area.