CKV_(dd): A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits

摘要

CMOS circuits consume great dynamic power in switching. It has been proposed that energy transfer through a rising V_(dd) dissipates small amounts of energy. In typical power gate circuits, the high-performance PMOS transistors (P_(sw)) that connect the circuit blocks to the power supply reduce leakage power by shutting off outer power (V_(dd)) to the idle blocks. We expand this technique by utilizing active Psw, which are turned on and off by clock signal. The P_(sw) w are fully turned on only for half of each clock cycle. This means that sufficient V_(dd) is provided to the circuit continuously for half of each clock cycle. In this manner, the circuit charge and discharge actions are cycle occur in different phases, and ramp V_(dd) is supplied to the designed circuit; we name this technique "CKV_(dd)." CKV_(dd) is a clock-controlled self-stabilized voltage technique, which generates stable ramp voltage to suppress the currents effectively. It is proposed to reduce dynamic power dissipation in conventional CMOS digital circuits. As compared to the conventional circuit, the circuits using CKV_(dd) technique possesses several characteristics that differ from those of the current circuits using constant V_(dd) power source. First, CKV_(dd) technique combines the power source and clock signal; it is an efficient low power technique. Second, CKV_(dd) propose a feasible method to generate ramp-V_(dd) and low- V_(dd). This technique would be convenient used to design generic low power digital circuits. Third, normal CMOS circuits show the dynamic power consumption increase proportional to the clock frequency. CKV_(dd) results in a lower-than-usual frequency dependency, it is suitable used to design high clock speed circuits. In investigating constant V_(dd) for MPEG VLD decoders, CKV_(dd)-circuit reduces 48% of the usual power dissipation and 88% of the usual peak current with small delay penalty.