3.3mW 11-times CMOS Frequency Multiplier

摘要

In wireless transceivers, frequency generation is main issue of signal transmission. Therefore, frequency synthesizer is required. Generally, PLL is used for frequency generation. However, PLL circuit consumes large power and occupies a large area. To improve the circuit properties, frequency multiplier is early reported. However, it has a problem that the circuit can not operate in high frequency. To overcome this problem, in this article new topology is proposed. The frequency multiplier was fabricated by a 90nm CMOS process. The core size is 7um by 4um. The power consumption of the circuit is 3.3mW with a 1.2V supply voltage and it operates as an 11-times frequency multiplier. However, a challengeable problem has been still left. We will mention it and also do future work to improve it.