Impact of Floating Body type DRAM with the Vertical MOSFET

摘要

Several kinds of capacitor-less DRAM cells based on planar SOI-MOSFET technology have been proposed and researched to overcome the integration limit of the conventional DRAM. In this paper, we propose the Floating Body type DRAM with the Vertical MOSFET and discuss its basic operation using a 3-D device simulator. In contrast to previous planar SOI-MOSFET technology, the Floating Body type DRAM with the Vertical MOSFET achieves a cell area of 4F~2 and its floating body cell by isolating the body from the substrate vertically by the bottom-electrode. Therefore, the necessity for a SOI substrate is eliminated. The basic memory operation of read, write, and erase for Vertical type 1 transistor (1T) DRAM is shown, and in addition, the retention and disturb characteristics of the Vertical type IT-DRAM is discussed.