An architecture for a nondeterministic distributed simulator

摘要

A computer architecture for an accelerated, parallel,nnondeterministic, discrete event simulator is described. The machine isnevaluated for accelerating: road traffic simulation. The architecturenemploys reconfigurable logic, systolic arrays, and a reduction bus tonperform microscopic discrete event simulation. The simulator, whichnachieves a speedup factor of at least 91 over its traffic softwarencounterpart, is fast enough to be practical to municipal trafficnmanagement engineers handling road incidents in large metropolitanntraffic networks