The limitations of methods to determine the dimensional offsets in VLSI processes are discussed. The authors give a straightforward quantitative analysis of those methods in which the number of measurement points is not greater than the number of unknowns in the equations. General equations are derived for errors that are made in the extraction of dimensional offsets of conducting layers and MOS transistors. It is shown that, due to a dramatic amplification of small deviations, large errors occur if the extraction is not done carefully. The analysis is applied to the determination of the width offset of conducting layers and to the determination of the MOS transistor channel length offset.
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