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首页> 外文期刊>IEEE Transactions on Semiconductor Manufacturing >Self-multiplexing force-sense test structures for (MOS) IC applications
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Self-multiplexing force-sense test structures for (MOS) IC applications

机译:适用于(MOS)IC应用的自多路复用力测试结构

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A self-multiplexing technique that enables multiple force-sense measurements to be carried out on test structures in the small area scribe lanes of product chips is presented. Instead of using separate address signals, the technique uses the distribution of stimulus and sense voltages across lines to select the proper test structure, leading to a drastic reduction in the number of probe pads. A simple, robust prototype circuit which enables four independent test structures to be measured with only five probe pads is presented. The technique can be extended to 12 structures with some additional circuitry. Excellent measurement accuracy is obtained and the self-multiplexing circuit allows a wide range of operating conditions while being insensitive to process variations.
机译:提出了一种自复用技术,该技术能够在产品芯片的小面积划片道上的测试结构上执行多次力感测。代替使用单独的地址信号,该技术使用跨线的激励和感测电压分布来选择适当的测试结构,从而大大减少了探针垫的数量。提出了一种简单,可靠的原型电路,该电路仅需五个探针垫即可测量四个独立的测试结构。该技术可以通过一些额外的电路扩展到12种结构。获得了极好的测量精度,并且自多路复用电路允许宽范围的工作条件,同时对过程变化不敏感。

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