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首页> 外文期刊>IEEE Transactions on Semiconductor Manufacturing >Reducing the cost variance in life testing of integrated circuits
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Reducing the cost variance in life testing of integrated circuits

机译:减少集成电路寿命测试中的成本差异

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摘要

The cost of life testing of integrated circuits (ICs) varies statistically. It is desirable to reduce the testing cost variance in order to reduce the chance of paying a testing cost that is much larger than the mean. In this paper, we study two methods for reducing the testing cost variance. The first method uses the technique of weighted sum of objective functions to integrate the objective of minimizing the mean testing cost and the objective of minimizing the testing cost variance. In the second method, the test engineer inspects the progress of life testing iteratively, collects failure information and then estimates the expected remaining testing cost. If this cost is unacceptably large, he replaces the failed ICs by the functioning ones and/or adds extra IC testers.
机译:集成电路(IC)的寿命测试成本在统计上有所不同。期望减少测试成本差异以减少支付比平均值大得多的测试成本的机会。在本文中,我们研究了两种减少测试成本差异的方法。第一种方法使用目标函数的加权总和技术来整合最小化平均测试成本的目标和最小化测试成本差异的目标。在第二种方法中,测试工程师反复检查寿命测试的进度,收集故障信息,然后估算预期的剩余测试成本。如果此费用过高,他将故障的IC替换为正常工作的IC,并/或增加额外的IC测试仪。

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