Finite element simulation of a stress history during themanufacturing process of thin film stacks in VLSI structures

摘要

High levels of interconnection line stress are a seriousnreliability problem for the integrated circuit industry. These stresses,nwhich are due to the thermal expansion coefficient difference betweennthe line and its surroundings, as well as to nonequilibrium film growth,ncan lead to failure mechanisms such as voiding and cracking.nHistorically, stresses in these lines have typically been modeled usingna fixed configuration at the final process step. The stresses arencalculated as the model Is cooled to room temperature. We have developednmodels to calculate stresses in interconnection structures as a functionnof process step, such as film deposition, etching, and thermal cycles.nDuring processing both thermal and intrinsic stresses are induced, andncontinuously changed by subsequent process steps. This paper presentsnsuch an analysis of simple interconnection structures which containntwo-level aluminum (Al) metal layers and a tungsten (W) via connection.nStress histories of the metal and via layers are obtained and discussed.nThis paper also discusses the effects on interconnection stress whennintrinsic stresses in various layers are taken into account