Modelling and Control of Backside-Induced ESD Defects During Wet-Chemical Processes in GaAs Front End Manufacturing

摘要

The semi-insulating characteristics of GaAs substrates makes GaAs front end manufacturing sensitive to ESD events occurring during wafer processing. Charges induced to the wafer by these ESD events can harm or even destroy insulating structures like MIM capacitors because these charges cannot dissipate. This paper deals with the modelling and control of backside-induced ESD defects on MIM capacitors. It will highlight how charges can be induced to the wafer from its backside by wet-chemical processes and consequently destroy MIM capacitors at the wafer front side. Furthermore, we will explain how the DI water resistivity is the root cause for these defects and how it can be controlled to prevent the creation of ESD defects.