A New Duty Cycle Control Strategy for Power Factor Correction and FPGA Implementation

摘要

The bottleneck of digital control for power factor correction (PFC) implementations is mainly due to three aspects: high calculation requirements, high cost, and limited switching frequency compared with analog implementations. A new duty cycle control strategy for boost PFC implementations is proposed in this paper. The duty cycle is determined based on the input voltage, reference output voltage, inductor current, and reference current. The duty cycle determination algorithm includes two terms, the current term and the voltage term, which can be calculated in parallel and requires only one multiplication and three additions (subtractions) operations in digital implementation. A 400-kHz switching frequency boost PFC based on field programmable gate array implementation and its test results show that the proposed new duty cycle control strategy has great potential in the next generation of high switching frequency PFC implementations, due to its lower calculation requirement, lower cost, and better performance than the conventional PFC control methods