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Analysis of SET Propagation in Flash-Based FPGAs by Means of Electrical Pulse Injection

机译:基于电脉冲注入的基于Flash的FPGA中SET传播分析

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摘要

Advanced digital circuits are increasingly sensitive to single event transients (SETs) phenomena. Technology scaling has resulted in a greater sensitivity to single event effects (SEEs) and more in particular to SET propagation, since transients may be generated and propagated through the circuit logic, leading to behavioral errors of the affected circuit. When circuits are implemented on Flash-based FPGAs, SETs generated in the combinational logic resources are the main source of critical behavior. In this paper, we developed a technique based on electrical pulse injection for the analysis of SETs propagation within logic resources of Flash-based FPGAs. We outline logic schematic that allows the injection of different SET pulses. We performed several experimental analyses. We characterized the basic logic gates used by circuits implemented on Flash-based FPGAs evaluating the effect on logic-chains of real lengths. Additionally, we performed an effective analysis evaluating the SET propagation through microprocessor logic paths. Results demonstrated the possibility of mitigating SET-broadening effects by acting on physical place and route constraints.
机译:先进的数字电路对单事件瞬态(SET)现象越来越敏感。技术缩放已导致对单事件效果(SEE)更加敏感,尤其是对SET传播更敏感,因为可能会通过电路逻辑生成并传播瞬变,从而导致受影响电路的行为错误。在基于闪存的FPGA上实现电路时,组合逻辑资源中生成的SET是关键行为的主要来源。在本文中,我们开发了一种基于电脉冲注入的技术,用于分析SET在基于Flash的FPGA的逻辑资源中的传播。我们概述了允许注入不同SET脉冲的逻辑示意图。我们进行了几次实验分析。我们对在基于Flash的FPGA上实现的电路所使用的基本逻辑门进行了表征,以评估对实际长度的逻辑链的影响。此外,我们进行了有效的分析,评估了SET在微处理器逻辑路径中的传播。结果表明,通过对物理位置和路线约束采取行动来减轻SET拓宽效应的可能性。

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