A Comparison of the SEU Response of Planar and FinFET D Flip-Flops at Advanced Technology Nodes

摘要

Heavy-ion experimental results were used to characterize single-event upset trends in 16 nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data show that 16 nm bulk FinFET flip-flops have considerably lower SEU cross sections than their sub-32 nm planar counterparts for linear energy transfer (LET) less than . However, FinFET SEU cross section improvement compared to the planar technologies is weak for high LET particles. Three-dimensional technology computer-aided design simulations are used to investigate charge collection mechanisms and single-event transient (SET) pulse widths at these advanced fabrication nodes. Simulation results show that SETs follow conventional scaling trends, which are that SET pulse widths reduce with technology scaling.