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首页> 外文期刊>IEEE transactions on nanotechnology >Crystalline ZrTiO$_{bf 4}$-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb$_{bf 2}$ O$_{bf 3}$ as a Passivation Layer
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Crystalline ZrTiO$_{bf 4}$-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb$_{bf 2}$ O$_{bf 3}$ as a Passivation Layer

机译:非晶态Yb $ _ {bf 2} $ O $ _ {bf 3} $作为钝化层的晶体ZrTiO $ _ {bf 4} $门控Ge金属-氧化物-半导体器件

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摘要

An amorphous Yb$_{2}$O $_{3}$ passivation layer integrated with a crystalline ZrTiO $_{4}$ film was explored as the advanced gate stack for Ge MOS devices. The ZrTiO $_{4}$/Yb$_{2}$O $_{3}$ gate stack demonstrates $D_{rm it}$ of 2.4 × 10$^{11}$ cm $^{-2}cdot, $eV$^{-1}$ and EOT down to 0.76 nm which are, respectively, due to the formation of an interfacial YbGeO $_{x}$ layer that well passivates the dangling bonds at Ge surface and the adoption of a crystalline ZrTiO$_{4}$ film with a κ value of 45.6. The gate stack also shows low leakage current, tight distribution of device parameters, and desirable reliability performance, paving an alternative avenue to develop high-performance Ge MOS devices.
机译:非晶Yb $ _ {2} $ O $ _ {3} $钝化层与晶体ZrTiO $ _ {4} $薄膜集成在一起的研究被用作Ge MOS器件的高级栅极叠层。 ZrTiO $ _ {4} $ / Yb $ _ {2} $ O $ _ {3} $门堆显示$ D_ {rm it} $为2.4×10 $ ^ {11} $ cm $ ^ {-2} cdot,$ eV $ ^ {-1} $和EOT分别低至0.76 nm,这是由于形成了界面YbGeO $ _ {x} $层,该层很好地钝化了Ge表面的悬空键并采用了结晶的ZrTiO $ _ {4} $薄膜,κ值为45.6。栅叠层还显示出低泄漏电流,器件参数紧密分布以及理想的可靠性能,为开发高性能Ge MOS器件铺平了道路。

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