An Ultra-Wideband Low Power-Consumption Low Noise-Figure High-Gain RF Power-Efficient DC–3.5-GHz CMOS Integrated Sampling Mixer Subsystem

摘要

An ultra-wideband CMOS integrated sampling mixer subsystem was designed and fabricated using Jazz Semiconductor''''s 0.18- $mu$m enhanced RF CMOS process. A two-stage switching strategy is implemented to synchronously merge a low-noise amplifier (LNA) with a sampler to achieve high gain, fast sampling, low noise figure, low power consumption, and enhanced RF power efficiency. The LNA and sample-and-hold capacitor are switched using two synchronized strobes generated on-chip. Characteristics of the sampling strobe, the sampling clock jitter, and their effects on the sampling bandwidth are discussed. Measured results show unprecedented performance of 9–12-dB voltage conversion gain, 16–25-dB noise figure, and power consumption of only 21.6 mW (with buffer) and 11.7 mW (without buffer) across dc to 3.5 GHz with 100-MHz sampling frequency.