Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver

摘要

A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demonstrated. The phase noise of the 24-GHz LO signal is $-$89 dBc/Hz at 1-MHz offset for a 400-Mb/s pseudo random binary sequence (PRBS) ${hbox{2}}^{31}-{hbox{1}}$ input. This first report of phase noise for a CDR is more than acceptable for amplitude shift-keying wireless communication systems with a square-law detector that is immune to the phase noise. The jitter of 400-MHz recovered clock is 2.6-ps rms (0.1% UI) for a PRBS ${hbox{2}}^{31}-{hbox{1}}$ input. The jitter performance is the best among the similar data rate $(sim{hbox{400}}~{hbox{Mb/s}})$ CDRs. The CDR bit error rate is less than ${hbox{10}}^{-13}$ .