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机译:具有SAR ADC PD的5GHz低功耗低噪声整数N数字子采样PLL
Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China;
Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China;
Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China;
Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China;
Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China;
Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China;
Phase locked loops; Delays; Capacitors; Clocks; Detectors; Phase noise; Quantization (signal);
机译:使用基于SAR-ADC的TDC的3.6 GHz低噪声小数N分频数字PLL
机译:使用双步混合ILFD和尾部耦合正交注入锁定振荡器的低功耗,低噪声毫米波二次采样PLL,用于IEEE 802.11ad
机译:通过校准频率偏差的5 GHz次采样基于PLL的扩频时钟发生器
机译:环形放大器在低功耗宽带数字二次采样ADC-PLL中的应用
机译:具有数字校准技术的低功耗高性能SAR ADC设计
机译:具有列并行12位SAR ADC的低噪声CMOS图像传感器的快速多重采样方法
机译:采用数字校准技术的低功耗高性能saR aDC设计