Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes

摘要

As multiple cell upsets (MCUs) become more frequent on SRAM memory devices, there is a growing interest on error correction codes that can correct multibit errors. Orthogonal Latin square (OLS) codes are an interesting option due to their low-complexity decoding and modular construction. Several works have also shown that it is possible to improve OLS codes, for example, by providing additional error correction for adjacent errors. In particular, a method has been recently proposed to implement triple adjacent error correction (TAEC) on double error correction (DEC) OLS codes. That scheme exploits the properties of OLS codes to achieve TAEC using an independent error correction logic and does not require additional parity check bits. This can be useful as, in many cases, the errors caused by MCUs are adjacent. In this paper, a more efficient technique to implement TAEC for DEC OLS codes is presented. The proposed method can be used as long as there are sufficient parity check bits to interleave among the data bits. This is the case for DEC OLS codes of up to 64 bits, which can be used to protect 16- and 64-bit data words. The new scheme uses an optimized bit placement that interleaves data and parity check bits to simplify the decoding. In particular, correction of single, double, and triple adjacent errors is now achieved with a single circuit that is a minor modification of the standard OLS decoding. This reduces area, power, and delay, making the new scheme attractive for circuit implementations.