A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 /spl mu/m NMOS devices

摘要

This paper reports a unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 /spl mu/m NMOS devices. As verified by the experimental data, the model shows an accurate prediction of the output conductance characteristics.