A cost-effective design for testability: clock line control and test generation using selective clocking

摘要

Clock line control (CLC) is proposed as a new design for testability technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. A novel sequential test generation technique for the circuits with CLC scheme is also presented. The new test generation methodology is able to selectively clock modules, expand multiple time frames for a sequential module and compose these local time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS'89 circuits, with and without CLC has been performed. Higher fault coverage in a shorter time has been achieved using test generation with CLC.