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Defect-Oriented Testing of RF Circuits

机译:射频电路的面向缺陷的测试

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摘要

Radio-frequency (RF) test cost is soaring due to the increasing complexity of RF devices. Radically new test approaches that enable test time reduction while ensuring product quality are needed to reduce the overall product cost. In this paper, we present a test development methodology for RF circuits based on novel parametric, open-circuit, and short-circuit defect models. We inject parametric defects as deviations in physical circuit parameters, such as resistances, transistor widths, and lengths, and inject open- and short-circuit defects into the critical locations that are derived from the layout using inductive fault analysis. Despite fault injection, we consider a circuit unacceptable only if it violates any one of the performance specifications. Our test development method aims at reducing not only the number of measurements but also the overall test hardware cost by incorporating the relative setup cost of each measurement into our selection criteria. Experimental results on an RF front-end device show that our test methodology reduces the test time by 50% and the number of test setups by 17% while identifying all unacceptable circuit instances with a 99% failure coverage without any yield loss.
机译:由于射频设备的复杂性不断提高,射频(RF)测试成本飞涨。全新的测试方法可以缩短测试时间,同时又能确保产品质量,从而降低了总体产品成本。在本文中,我们提出了一种基于新型参数化,开路和短路缺陷模型的射频电路测试开发方法。我们将参数缺陷注入为物理电路参数(例如电阻,晶体管宽度和长度)中的偏差,并使用感应式故障分析将开路和短路缺陷注入到从布局派生的关键位置。尽管注入了故障,但仅在电路违反任何一项性能规格时,我们才认为该电路是不可接受的。我们的测试开发方法旨在通过将每次测量的相对设置成本纳入我们的选择标准,不仅减少测量数量,而且减少总体测试硬件成本。在RF前端设备上的实验结果表明,我们的测试方法将测试时间减少了50%,并将测试设置的数量减少了17%,同时识别了所有不可接受的电路实例,其故障覆盖率达到了99%,而没有任何良率损失。

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