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Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data

机译:贝叶斯模型融合:通过重用早期数据对模拟和混合信号电路进行大规模性能建模

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摘要

Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian model fusion (BMF) to address this challenge. The key idea of BMF is to borrow the information collected from an early stage (e.g., schematic level) to facilitate efficient performance modeling at a late stage (e.g., post layout). Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Furthermore, to make the proposed BMF method of practical utility, four implementation issues, including: 1) prior mapping; 2) missing prior knowledge; 3) fast solver; and 4) prior and hyper-parameter selection, are carefully considered in this paper. Two circuit examples designed in a commercial 32 nm CMOS silicon on insulator process demonstrate that the proposed BMF method achieves up to $9times $ runtime speed-up over the traditional modeling technique without surrendering any accuracy.
机译:由于存在高维变化空间和昂贵的电路仿真,当今的模拟和混合信号电路的有效性能建模是一项重要而又具有挑战性的任务。在本文中,我们提出了一种新颖的性能建模算法,称为贝叶斯模型融合(BMF),以解决这一挑战。 BMF的主要思想是借用从早期阶段(例如,原理图级别)收集的信息,以促进在后期阶段(例如,后期布局)进行有效的性能建模。通过贝叶斯推断对早期和晚期阶段之间的性能相关性进行统计建模,可以实现此目标。此外,为了使所提出的BMF方法具有实用性,存在四个实现问题,包括:1)事先映射; 2)缺少先验知识; 3)快速求解器;和4)优先考虑和超参数选择,在本文中进行了仔细考虑。在商用32纳米CMOS绝缘体上工艺中设计的两个电路示例表明,与传统的建模技术相比,所提出的BMF方法可实现高达9倍的运行时间加速,并且不降低精度。

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