首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing
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OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing

机译:OWARU:具有关键路径平滑功能的自由空间感知时序驱动增量放置

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摘要

This paper presents an incremental timing-driven placement tool, named OWARU. It optimizes timing critical paths through a free space-aware path smoothing: the gates on such paths are relocated to free spaces around the smoothed paths, while incremental static timing analysis is involved to accurately assess timing changes due to the relocation. OWARU is extended to accommodate gate sizing and layer assignment to demonstrate the effectiveness of unified physical synthesis optimizations and incremental placement. The goal is to show that OWARU is an ideal platform for timing closure at later stages of a physical design flow. OWARU is applied on a set of test circuits from 14-nm high-performance commercial microprocessors, which originally failed in timing closure. On average, the worst slack is improved by 63.6%, which corresponds to 5.0% of the clock period; total negative slack is improved by 69.1%.
机译:本文介绍了一种名为OWARU的增量时序驱动放置工具。它通过可感知空间的自由路径平滑来优化时序关键路径:将此类路径上的门重新放置到平滑路径周围的自由空间中,同时使用增量静态时序分析来准确评估由于重定位导致的时序变化。 OWARU进行了扩展,以适应门的大小调整和层分配,以演示统一物理综合优化和增量放置的有效性。目的是表明OWARU是在物理设计流程的后续阶段进行时序收敛的理想平台。 OWARU被应用于14纳米高性能商用微处理器的一组测试电路上,这些测试电路最初在时序收敛方面失败。平均而言,最差的松弛改善了63.6%,相当于时钟周期的5.0%;总负松弛度提高了69.1%。

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