首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs
【24h】

Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs

机译:带有分流开路短截线的可切换真时延(TTD)线的计算机辅助设计

获取原文
获取原文并翻译 | 示例
           

摘要

This paper presents a new technique to design switchable true time delay (TTD) lines using periodic shunt open-stubs, shorter than a quarter wavelength at the highest frequency of interest. Structural parameters are obtained by minimizing the group delay variation and maximizing the return loss over the operating band. Advantages of the proposed design are low insertion loss, higher 1 dB compression point, and less number of switches compared to the conventional designs. To verify the proposed technique, 2-states and 8-states TTD lines are fabricated for L- and S-band applications. For the 8-states delay networks, measured insertion losses are smaller than 1.9 dB at 3 GHz. Return losses are more than 10 dB over 1-4 GHz band. Measured maximum time delay is 84 ps for the 8-states delay lines with a step size of 10 ps. All the TTDs operate as linear device at least up to 23 dBm.
机译:本文提出了一种新技术,该技术可使用周期性分路开路短截线设计可切换的真实时间延迟(TTD)线路,在感兴趣的最高频率下短于四分之一波长。通过最小化群时延变化并最大化工作频带上的回波损耗来获得结构参数。与常规设计相比,所提出设计的优点是低插入损耗,更高的1 dB压缩点和更少的开关数量。为了验证所提出的技术,制造了用于L波段和S波段应用的2状态和8状态TTD线。对于8状态延迟网络,在3 GHz时测得的插入损耗小于1.9 dB。在1-4 GHz频带上,回波损耗超过10 dB。对于8状态延迟线,步长为10 ps,测得的最大时间延迟为84 ps。所有TTD都至少在23 dBm时作为线性器件工作。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号