Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors

摘要

A low-voltage BiCMOS four-quadrant multiplier using triode-region transistors is presented, this circuit has been fabricated in a 1.0 /spl mu/m BiCMOS process. Experimental results show that for a power supply of /spl plusmn/1.5 V, the linear range is over /spl plusmn/0.6 V with the linearity error of less than 2%. The total harmonic distortion is less than 2% with an input range up to /spl plusmn/0.6 V. The measured -3-dB bandwidth of this proposed BiCMOS multiplier is about 10 MHz. This circuit is expected to be useful in low-voltage analog signal-processing applications.