Iterative Gain Enhancement in an Algorithmic ADC

摘要

This paper presents a 14.9-bit 3.57-MS/s algorithmic ADC that uses iterative gain enhancement, a technique that uses multiple clock phases to increase the effective op-amp gain in a switched-capacitor circuit. Using an op-amp that gives only 30-dB loop gain in a feedback circuit without gain enhancement, application of the iterative gain enhancement technique boosts the loop gain to 81 dB. The algorithmic ADC uses a capacitor sharing and scaling technique, which saves power and reduces errors. The ADC has an active area of 0.75 in 0.25- CMOS and dissipates 16.2 mW. Iterative gain enhancement increases the SNDR from 44.6 dB to 78.5 dB and the SFDR from 45.9 dB to 96.2 dB. Reducing the number of gain-enhancement iterations for the LSBs increases the conversion rate from 3.57 MS/s to 4.65 MS/s with only minor performance degradation.