Iterative Gain Enhancement in a Power-Efficient Algorithmic ADC.

摘要

Switched-capacitor (SC) circuits are commonly used in applications such as data conversion and filtering. With low supply voltages and low intrinsic transistor gain in modern CMOS processes, building high-gain op amps that are needed in accurate switched-capacitor circuits is difficult. As technology becomes more advanced, fT increases, which makes op amps faster. However, more advanced processes also give reduced intrinsic transistor gain, and this trend increases errors in feedback circuits. A number of switched-capacitor gain-enhancement techniques exist, which increase the accuracy of op-amp-based circuits by storing the state of the circuit on a capacitor and using the voltage on this capacitor during extra clock phases to correct the output. However, previous SC gain-enhancement techniques achieve limited effective gain.;This dissertation presents iterative gain enhancement, a technique that uses multiple clock phases to increase the effective op-amp gain in a switched-capacitor circuit to more than can be achieved with a single application of gain enhancement. Using an op amp that gives only 30-dB loop gain in a feedback circuit without gain enhancement, application of the iterative gain enhancement technique boosts the loop gain to 81 dB.;A prototype algorithmic analog-to-digital converter (ADC) was designed, fabricated and tested to demonstrate iterative gain enhancement. The algorithmic ADC uses a capacitor sharing and scaling technique, which saves power and reduces errors. The ADC has an active area of 0.75 mm2 in 0.25-μm CMOS and dissipates 16.2 mW of power. Iterative gain enhancement increases SNDR from 44.6 dB to 78.5 dB and SFDR from 45.9 dB to 96.2 dB. Reducing the number of gain-enhancement iterations for the LSBs increases the conversion rate from 3.57 MS/s to 4.65 MS/s with only minor performance degradation.