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A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System

机译:用于可编程流体处理器系统的高压SOI CMOS激励器芯片

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A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode wave- form frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.
机译:高压(HV)集成电路已被证明可在其疏水涂层表面上的驱动电极阵列上的可编程路径上传输流体液滴样本。该激励器芯片是基于介电泳(DEP)的微流体芯片实验室系统的引擎,可产生场激励,将流体液滴注入操纵表面并在其附近移动。该芯片的架构可扩展至N X N个相同的HV电极驱动器电路和电极的阵列。激励器芯片在几种意义上都是可编程的。多个液滴的路径可以在电极阵列的边界内任意设定。可以基于系统配置和操纵特定液滴成分所需的信号来调整电极激励波形的电压幅度,相位和频率。电极激励波形的电压幅度可以从最小逻辑电平设置到制造技术的击穿电压的最大极限。电极激励波形的频率也可以独立于其电压进行设置,最大取决于所驱动液滴的类型。可以对激振器芯片进行涂层处理,并将其氧化物表面用作液滴操作表面,也可以将其与由各种材料组成的顶部安装的封闭式流体室一起使用。励磁芯片的HV功能使所产生的DEP力渗透到封闭的腔室区域中,并且可调节的电压幅度可以适应各种腔室底板厚度。该演示激励器芯片具有32 x 32的标称100 V电极驱动器阵列,可在过程中的每个时间点分别对两个相位中的任意一个进行编程:相对于参考时钟为0deg和180deg。对于此演示芯片,在以100V峰峰值周期波形操作电极时,最大HV电极波形频率约为200 Hz;而最大HV波形频率约为200 Hz。标准的5V CMOS逻辑数据通信速率最高可变化250 kHz。该HV演示芯片采用130V 1.0微米SOI CMOS制造技术制造,最大耗散1.87 W,约为10.4 mm x 8.2 mm。

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