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Implementation studies for a VLSI Prolog coprocessor

机译:VLSI Prolog协处理器的实施研究

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A 32-bit coprocessor designed as one VLSI (very large-scale integrated) circuit that is based on microprogrammed architecture is described. The most innovative aspect of this project is the fully dedicated microarchitecture of the execution unit. A detailed analysis was carried out by considering two execution techniques, 'interpreted' and 'compiled', and the computational model and its implementation were simulated to support the final design decisions. A description is given of compiled execution, which was selected for the final design. The simulations trace the actual behavior of the execution model and point out the performance that can be obtained using different architectural solutions. The results permit the selection of an optimal architecture within the technological constraints of VLSI implementations.
机译:描述了一个32位协处理器,该协处理器被设计为一个基于微程序架构的VLSI(超大规模集成电路)电路。该项目最具创新性的方面是执行单元的完全专用的微体系结构。通过考虑“解释”和“编译”两种执行技术进行了详细分析,并对计算模型及其实现进行了仿真,以支持最终的设计决策。给出了编译执行的说明,该说明被选择用于最终设计。仿真跟踪执行模型的实际行为,并指出可以使用不同的体系结构解决方案获得的性能。结果允许在VLSI实现的技术限制内选择最佳架构。

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