A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches

摘要

The resiliency problem of die-stacked memory will become important because of its lack of serviceability. This article details how to provide practical and cost-effective reliability, availability, and serviceability support for die-stacked DRAM cache architectures. The proposed approach can provide varying levels of protection, from fine-grained single-bit upsets to coarser-grained faults within the constraints of commodity non-error-correcting code DRAM stacks.