A bit-slice architecture for sigma-delta analog-to-digital converters

摘要

The sigma-delta analog-to-digital converters is based on filtering and undersampling by the digital section of the one-bit output stream coming from the modulation. The structure of this section, consisting of a sine cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that from both signal processing and hardware implementation viewpoints it is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It can be easily expanded when higher bit resolutions are required.