Novel serial--parallel multipliers

摘要

New designs of serial parallel multipliers based on the modified Booth and multi-bit recoding algorithms ale introduced. Using recoding for the parallel operand. two proposed systolic multipliers have been introduced to build structures having n/2 and n/3 cells. The proposed serial parallel multipliers are compared with other structures on the basis of multiplication time, area, and complexity. By using multi-bit overlapped recoding of the multiplier operand. the multiplier operates at twice the speed of the existing designs and has a much lower AT~2 complexity.