Novel CMOS operational amplifier design technique for high-frequency switched-capacitor applications

摘要

Presents a design technique that enhances the operational characteristics of CMOS operational amplifiers for high-frequency switched-capacitor applications. The design approach introduces a method of settling time reduction that uses predefined layout blocks that can be placed side by side to perform the desired topological scaling for minimum settling time against load capacitance. Further, the method lends itself well with the current CAE tools available which perform cell placement and interconnect routing. This technique allows a designer to quickly implement an operational amplifier that is optimised in an AC sense for a required load capacitance. Simulation results are presented that demonstrate a possible enhancement in performance of up to 400%.