一种新型高速CMOS全差分运算放大器设计

摘要

A low-voltage high-speed CMOS fully-differential operational amplifier based on the pipelined ADC was designed. The operational amplifier combining the amplifying structure of folded cascode with a novel continuous time CMFB circuit achieves high speed and high stability. The Spectre simulation of the operational amplifier is implemented on the basis of SMIC 0. 25 ? M CMOS standard process model under Cadence. At the voltage of 2. 5 V single power supply, the open loop DC gain is 71. 1 dB, the unity gain bandwidth is 303 MHz, the phase margin is 52°, the slew rate is 368. 7 V/μs and the settling time is 12. 4 ns while the load capacitance is 0. 5 pF.%设计了一种基于流水线模/数转换系统应用的低压高速CMOS全差分运算放大器.该运放采用了折叠式共源共栅放大结构与一种新型连续时间共模反馈电路相结合以达到高速度及较好的稳定性.设计基于SMIC0.25μmCMOS标准工艺模型,在Cadence环境下对电路进行了Spectre仿真.在2.5V单电源电压下,驱动0.5pF负载时,开环增益为71.1dB,单位增益带宽为303MHz,相位裕度为52°,转换速率高达368.7V/μs,建立时间为12.4ns.