Novel analogue CMOS defuzzification circuit

摘要

An analogue CMOS circuit technique for the implementation of defuzzification is proposed. The defuzzification method is based upon the normalisation locked loop (NLL) method, but with two key improvements: the compact representation of triangular membership functions, and a mechanism to ensure that the relative rule weight proportions are preserved during normalisation. Circuit complexity is considerably reduced by combining these two operations in a single circuit stage. The proposed weight circuit, which evaluates normalised rule weights, has been realised using current squaring circuits proposed by Bult and Wallinga (1987). The weight circuit has been fabricated in a 2.0 mu m CMOS process. Results obtained from the fabricated circuit operating as part of a NLL are presented.