The advent of analogue and hybrid VLSI circuits has created newnrequirements for the design of many previously known building blocks.nFor example, implementation of cascaded multilayer analogue/hybridnneural networks requires output drivers that can charge the large numbernof interconnecting lines, and remain stable in the presence of largencapacitive loads. A CMOS high dynamic range, high-drive buffer suitablenfor driving large capacitive loads is presented in this paper. Annarea-efficient output stage has been used, with which a rail-to-railndrive capability into a 5000 pF load at 160 kHz is achieved. The circuitnoccupies only 110 mils2 in a 3 Μm technology. The outputnrange is rail to rail for R>10 kΩ. The buffer is capable ofndriving resistive loads down to 300 Ω with acceptable THD
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