Owing to the ever-increasing clock frequency in digital circuits and systems, simultaneous switching noise (SSN), caused by fast rise/fall pulse edges in combination with parasitic inductance in the power supply distribution network, is becoming a severe problem in many high-speed digital system designs. It is quantitatively shown that the influence of SSN, which is negligible when the rise/fall time is long (<5 ns), becomes a critical factor, limiting system performance in the subnanosecond rise time region. Based on theoretical analyses and computational simulations in respect to various packaging techniques, technical solutions and design guidelines for reducing SSN are summarised.
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