Designing the topology of a clock distribution network isnconsidered for a synchronous digital integrated circuit so as to satisfyna nonzero clock skew schedule. A methodology and related algorithms fornsynthesising the topology of the clock distribution network from a clocknschedule derived from circuit timing information are presented. A newnformulation of the problem of designing the clock distribution networknis given as an efficiently solvable integer linear programming problem.nThe approach is demonstrated on the suite of ISCAS'89 benchmarkncircuits. Up to 64% performance improvement is attained on thesencircuits by exploiting nonzero clock skew throughout the synchronousnsystem. Clock tree topologies that implement the nonzero clock skewnschedule based on the synthesis algorithms presented are described forneach of the benchmark circuits
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