METHOD FOR CLOCK TREE SYNTHESIS AND METHOD FOR FORCASTING THE EFFECT OF CLOCK TREE SYNTHESIS

摘要

PURPOSE: A method for synthesizing a clock tree and an estimating method of a clock tree synthesis effect are provided to synthesize the clock tree in case that a gated clock or a multi-clock source is present, and previously obtain the information for the clock tree synthesis effect before a layout process. CONSTITUTION: A clock route is fixed and a clock net is analyzed(S3). If a problem occurs in the clock tree synthesis, the clock net is analyzed again by setting a user synchronization pin and a user ignorance pin(S5). If not, an automatic clock tree cell is inserted(S6). A delay time is calculated by using the inserted clock tree cell(S7). The timing is verified before the layout by using a calculation result(S8). If a verification result is normal, an information file for the clock tree synthesis is output(S9). The clock tree synthesis is performed on the layout(S10).