The implementation of multi-carrier code division multiple accessn(MC-CDMA) receivers in digital hardware is considered. A low powernalgorithm is proposed which treats the received signal as a block ofnsymbols, rather than processing the symbols individually. This reducesnpower by holding one input to the multiplier circuits used in thenmulti-carrier combiner multiplication constant for a number of clockncycles. This produces a 50% reduction in power consumption for anmulti-user detection combiner circuit. This algorithm is also extendednto the fast Fourier transform (FFT) block and allows an overall powerndrain reduction of 13% for the whole receiver. A software configurablenversion of the circuit, which allows a trade-off between power reductionnand processing delay, is also described
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