VLSI Architecture of Switching Median Filter for Salt and Pepper Noise Removal

摘要

In this paper, VLSI architecture of new switching based median filter to remove high density salt and pepper noise in digital images is proposed. The absolute difference between center pixel and the median of trimmed array obtained from a 3 × 3 sliding window is compared with the predefined threshold value to identify the pixel is noisy or not. In the filtering stage, the noisy pixels are replaced by median of noise free pixels in the 3×3 filtering window. The experimental results for various test images show that the performance of the proposed algorithm is superior to existing algorithms, namely SMF, ACWMF, TMF, PWMAD, ARWMF, REBF, MDBUTMF and NAWMF in terms of visual quality and edge preservation. The proposed algorithm is also implemented with VHDL and simulated using Xilinx 10.1. The quantitative analysis in terms of logic elements, power and delay are observed in Altera Quartus Ⅱ and compared with existing state of art algorithms, namely SMF, DBA, Parallel sorting, REBF, MDBUTMF and NAWMF.