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All Digital Spread Spectrum Modems for Power Line Communications

机译:用于电力线通信的所有数字扩频调制解调器

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Through the use of band-spreading techniques electrical power distribution networks become reliable and universal data links. For cost and performance reasons all digital solutions for the construction of modems are paramount. The use of general purpose digital signal processors (DSP) is neither feasible nor cost-effective. After a review of appropriate signalling schemes the key components for integration into an ASIC will be outlined. Within the transmitter section of the ASIC a programmable address counter together with a sample memory provides precise and fast signal synthesis. In the receiver section a fast front-end is needed for correlation operations. Furthermore essential steps towards bit decision are performed. A typical ASIC, representing the heart of a power line modem, finally contains the following functional blocks: An 8 bit correlator with a minimum of four separate accumulators, a squarer with at least two additional accumulators forming the decision logic, and a programmable 10 bit address counter. VHDL-based ASIC design was performed and fabrication took place in October 1994 within the EUROCHIP project. An ASIC incorporates 5250 gates with a power consumption below 50 mW. Modems have been built with different signalling schemes for data rates up to 2400 bits/s. Measurements revealed typical bit error rates below 10~(-6).
机译:通过使用频带扩展技术,配电网络成为可靠的通用数据链路。由于成本和性能的原因,所有用于调制解调器的数字解决方案都是至关重要的。通用数字信号处理器(DSP)的使用既不可行也不具有成本效益。在审查了适当的信令方案之后,将概述集成到ASIC中的关键组件。在ASIC的发送器部分中,可编程地址计数器与采样存储器一起提供了精确而快速的信号合成。在接收器部分,需要一个快速的前端进行关联操作。此外,执行朝向位决策的基本步骤。代表电力线调制解调器核心的典型ASIC最后包含以下功能块:一个8位相关器,其中至少有四个独立的累加器;一个平方器,其中至少有两个额外的累加器构成决策逻辑;一个可编程的10位地址计数器。基于VHDL的ASIC设计已于1994年10月在EUROCHIP项目中进行制造。 ASIC包含5250个门,功耗低于50 mW。使用不同的信令方案构建的调制解调器的数据速率高达2400 bit / s。测量表明典型的误码率低于10〜(-6)。

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