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A signal processing ASIC for an all digital spread spectrum modem for power line communications

机译:用于全数字扩频调制解调器的信号处理ASIC,用于电力线通信

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Through the use of spread spectrum techniques low voltage electrical power distribution networks become reliable and universal digital data links. After a short review of appropriate signalling schemes the paper will outline the basic ideas leading to the construction of an ASIC. It is shown that this step has to be taken because the use of general purpose digital signal processors (DSP) is neither feasible nor cost-effective. The design of the transmitter section into an ASIC is relatively easy. An inexpensive counter with a reset-to-zero feature operates as the core element for precise and fast signal synthesis. Signal selection and timing control are performed by an on-board microcontroller. The solution for receiver signal processing is more complicated. A fast signal processing front end is needed which does correlation operations based on a MAC structure (multiply and accumulate). The mentioned on-board microcontroller performs bit decision, serial data transfer as well as timing and control functions. Investigations revealed that a word length of 8 bit is sufficient in the transmitter as well as in the receiver section of a typical power line modem. Finally the ASIC has to contain the following functional blocks: an 8 bit MAC unit with at least four separate 32 bit accumulators, a microcontroller interface, a 9 bit programmable counter, and a clocking and control unit. ASICs according to the outlined scheme were designed and fabricated in spring 1993 using a 0.8 /spl mu/m BiCMOS full custom process. Testing revealed a power consumption of less than 5 mW at the full operating speed of 12 MHz. Half-duplex modems are under construction with different signalling schemes for data rates up to 2400 bits/s. First measurements revealed a bit error rate at typical indoor installations in the range of 10/sup -5/. Further work will concentrate on outdoor applications such as remote meter reading as well as control and supervision of consumer's premises.
机译:通过使用扩频技术,低压配电网络成为可靠的通用数字数据链路。在简短回顾了适当的信令方案之后,本文将概述导致构建ASIC的基本思想。结果表明必须采取这一步骤,因为使用通用数字信号处理器(DSP)既不可行也不具有成本效益。将发送器部分设计为ASIC相对容易。具有复位至零功能的廉价计数器用作精确和快速信号合成的核心元素。信号选择和时序控制由板载微控制器执行。接收器信号处理的解决方案更加复杂。需要一个快速的信号处理前端,该前端基于MAC结构(相乘和累加)进行相关运算。提到的板载微控制器执行位决策,串行数据传输以及定时和控制功能。调查表明,在典型的电力线调制解调器的发送器和接收器部分,8位的字长就足够了。最后,ASIC必须包含以下功能块:具有至少四个单独的32位累加器的8位MAC单元,微控制器接口,9位可编程计数器以及时钟和控制单元。根据概述的方案的ASIC是在1993年春季使用0.8 / splμm/ m的BiCMOS完全定制工艺设计和制造的。测试表明,在12 MHz的全部工作速度下,功耗不到5 mW。半双工调制解调器正在构建中,具有不同的信令方案,数据速率高达2400 bit / s。首次测量显示,在典型的室内安装中,误码率在10 / sup -5 /范围内。进一步的工作将集中在户外应用,例如远程抄表以及对用户房屋的控制和监督。

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