Design methodologies for C-2C ladder-based D/A convertors for PCM codecs

摘要

The paper is devoted to the analysis and design of C-2C ladder-based D/A convertors. First, it is shown that the conventional unit capacitor bottom plate parasitics result in unacceptability high (<0.5 LSB) nonlinearity of C-2C ladder D/A convertors. To this end, a unit capacitor C to proposed, which has linear floating bottom plate parasitics C/sub p/. Two design approaches to 'design in' the linear parasitics are developed, one based on the assumption that C/sub p/C and the other assuming C/sub p//C=10%, culminating in 7-bit designs with nonlinearity as low as 0.095.LSB. These 7-bit designs are then extended to 13 bits, which are adequate for designing both A- and mu -law PCM codecs.