Linear-testable and C-testable N/sub /spl times//N/sub y/ modified Booth multipliers

摘要

The testability of modified Booth multipliers is examined with respect to the cell fault model, an implementation-independent fault model. This is especially useful in design environments where the cell realisations are unknown. First, a linear-testable multiplier is proposed which can be tested with 2N/sub x/+[Ny/2]+40 test vectors and requires only primary input, Zero delay negligible hardware overhead is imposed. Then, a C-testable multiplier is proposed which can be tested with 70 test vectors and requires only two extra primary inputs. Both the hardware and delay overheads are very small and decrease rapidly with increasing N/sub x/ or N/sub y/. The linear-testable design is superior to the C-testable one, for small multipliers since it requires less test vectors in addition to the much smaller hardware overhead and zero delay overhead it imposes. For larger multipliers there is a trade-off between the number of test vectors, which is smaller for the C-testable design, and the overheads, which are smaller for the linear-testable design.